In the field of digital audio circuits or the like, a digital-to-analog conversion circuit in which an input digital signal of m bits is digital-to-analog converted by using a D/A converter having parallel input terminals of n bits (n&lt;m) makes the circuit inexpensive. FIG. 4 shows an example of such a conventional D/A conversion circuit.
In FIG. 4, parallel data consisting of m bits is passed through input terminals 1.sub.l -1.sub.m. The most significant bit (MSB) representing the polarity of the data is directly applied to an input of a D/A converter 2, the second through n-th bits are applied respectively to a first set of inputs to switches SW.sub.1 -SW.sub.n-1 of a selector 3, and the (m-n)-th from the second bit, i.e., the (2+m-n)th bit, through the m-th or least significant bit (LSB) are applied respectively to a second set of inputs to the switches SW.sub.1 -SW.sub.n-1. The MSB and the (n-1) bits passed through the selector 3 are converted into analog data in the D/A converter 2 which has n parallel input bit terminals. After being selectively level-controlled by a variable gain amplifier 4, the analog data provided by the D/A converter 2 is output from the amplifier 4 as an analog output. The D/A converter 2 starts D/A conversion in response to a start instruction signal supplied through an input terminal 5.
Several of the most significant bits of the m bits of parallel data, for example, the upper three bits which are not provided as second inputs to switches SW.sub.1 through SW.sub.n-1, are also supplied to a level detector 6. Weighting of the respective parallel data is determined by the code logic of the respective bits. Therefore, if the codes of the upper three bits are encoded by the level detector 6 constituted, for example, by an EX-OR circuit, it is possible to detect the signal level of an input digital signal with respect to a set level determined by the upper three bits of the input digital signal. The level detector 6 generates a detection output when the signal level of the input digital signal is lower than the set level. The detection output triggers a retriggerable monostable multi-vibrator (hereinafter abbreviated as retriggerable MMV) 7. The output of the retriggerable MMV 7 is used as a control signal for switching the contacts of the switches SW.sub.1 -SW.sub.n-1 and for changing the gain of the variable gain amplifier 4.
In this arrangement, when the signal level of the input digital signal is higher than the set value, no control signal is generated from the retriggerable MMV 7 so that the switches SW.sub.1 -SW.sub.n-1 constituting the selector 3 are maintained in the state as illustrated in the drawing and the gain of the variable gain amplifier 4 is not changed. Accordingly, the n bits consisting of the MSB and the next (n-1) most significant bits are applied to the D/A converter 2 so that the data is converted to an analog output.
When the signal level of the input digital signal is lower than the set value, on the other hand, the respective contacts of the switches SW.sub.1 -SW.sub.n-1 of the selector 3 are switched to the lower positions in the drawing in response to the control signal of the retriggerable MMV 7. Thus, the LSB and the next (n-1) least significant bits are all shifted toward the MSB by (m-n) bits, e.g.. two bits in the illustrated example, and these n least significant bits are applied to the D/A converter 2 together with the data of the MSB. At the same time, the gain of the variable gain amplifier 4 is changed to a lower value in response to the control signal of the retriggerable MMV 7 and the signal level of the output analog signal is attenuated by a value corresponding to the increase in the digital data value caused by the above-mentioned 2-bit data shift. As a result, the signal level of the output analog signal will correspond to that of the original digital data value. In this case, as shown in FIG. 5, the retriggerable MMV 7 has a predetermined delay time t.sub.0, so that the state of the switches SW.sub.1 -SW.sub.n-1 and the gain of the variable gain amplifier 4 are changed when no input digital signal having a signal level higher than or equal to the set level exists during the waiting time t.sub.0.